Week 2 — Resistive Circuit Analysis: KCL, KVL, Nodal, Mesh, Thévenin, and Norton

Overview

Given any network of resistors and sources, there is a small set of mechanical procedures that will always find every voltage and current. This week is about making those procedures — nodal analysis, mesh analysis, superposition, and source transformation — completely automatic, and then proving the two equivalent-circuit theorems (Thévenin and Norton) that let you collapse an arbitrarily complicated linear box into two numbers. Equivalent circuits are not a convenience; they are how every later block in this course is reasoned about. A sensor’s output impedance, an amplifier’s input impedance, a filter driving a load — all are Thévenin equivalents talking to each other.

The bench goal is to prove these abstractions are real. You will build a multi-resistor network, measure its open-circuit voltage and short-circuit current at a port, compute the Thévenin equivalent, then build that two-resistor equivalent and show it is indistinguishable from the original under load. When the equivalent and the original give the same load voltage for every load, the abstraction has earned your trust — and you will lean on it for the rest of the course.

This week assumes Week 1’s Ohm’s law and the lumped model are automatic. It feeds Week 3 (the same KCL/KVL apply once $i$–$v$ relations become differential) and is the conceptual basis for output/input impedance reasoning in Weeks 5–7.

Readings

CAD Ch. 2: Series/parallel reduction, the voltage divider and current divider, and Δ–Y conversion. Extract: when reduction is faster than full nodal analysis, and the divider formulas you will use hundreds of times.
CAD Ch. 3: Nodal analysis, mesh analysis, superposition, source transformation, Thévenin and Norton equivalents, and maximum power transfer. Extract: a reliable algorithm for each, and the proof that any linear two-terminal network has a Thévenin equivalent.
PEI Ch. 2 (Kirchhoff, divider, Thévenin sections): The same theorems in working-engineer language, with the practical caveats (real source resistance, loading). Extract: how loading changes a divider’s output.

Key Concepts

Kirchhoff’s laws as conservation statements

KCL (current law): the algebraic sum of currents into any node is zero, $\sum_k i_k = 0$. This is charge conservation plus the lumped assumption that no charge accumulates at a node. KVL (voltage law): the algebraic sum of voltage drops around any closed loop is zero, $\sum_k v_k = 0$. This is the path-independence of potential, i.e. $\oint \mathbf{E}\cdot d\boldsymbol{\ell}=0$ when flux is negligible. Every analysis method below is just an organized way of writing these two laws plus Ohm’s law.

Series, parallel, and the divider formulas

Resistors in series add; in parallel the conductances add:

\[ R_\text{series}=\sum_i R_i, \qquad \frac{1}{R_\text{parallel}}=\sum_i \frac{1}{R_i}, \qquad R_1\parallel R_2 = \frac{R_1 R_2}{R_1+R_2}. \]

The voltage divider (series resistors, output across one of them) and current divider (parallel resistors):

\[ v_j = v_\text{in}\,\frac{R_j}{\sum_i R_i}, \qquad i_j = i_\text{in}\,\frac{G_j}{\sum_i G_i} = i_\text{in}\,\frac{R_\text{other}}{R_1+R_2}. \]

The divider is the single most-used circuit in analog design. Its central caveat: the formula assumes no load on the output. Connecting a load $R_L$ across $R_2$ replaces $R_2$ with $R_2\parallel R_L$ and pulls the output down — the source of countless real bugs (Week 7 op-amp buffers exist largely to fix this).

Nodal analysis

Pick a reference (ground) node. For each remaining node, write KCL with branch currents expressed via Ohm’s law in terms of node voltages. This yields a linear system $\mathbf{G}\mathbf{v}=\mathbf{i}$, where $\mathbf{G}$ is the conductance matrix (symmetric for resistive networks: diagonal = sum of conductances at the node, off-diagonal = $-$shared conductance), $\mathbf{v}$ the unknown node voltages, and $\mathbf{i}$ the source-current vector. Nodal analysis is the method SPICE-family engines like ngspice use internally (modified nodal analysis), which is why simulating and hand-solving should agree exactly for linear circuits.

Mesh analysis

The dual: for planar circuits, assign a loop (“mesh”) current to each window and write KVL around each, giving $\mathbf{R}\mathbf{i}=\mathbf{v}$. Choose nodal when there are fewer nodes than meshes, mesh when the reverse — both give identical answers. Doing one problem both ways is the best way to confirm you have not made a sign error.

Superposition

In a linear network, the response to multiple independent sources is the sum of the responses to each source acting alone (other voltage sources shorted, current sources opened). Superposition is a direct consequence of linearity and is the conceptual seed of frequency-domain analysis: in Week 8 we superpose sinusoids (Fourier) instead of DC sources. It does not apply to power (which is quadratic) — a frequent mistake.

Thévenin and Norton equivalents

Theorem: any linear two-terminal network is externally indistinguishable from a single voltage source $V_\text{th}$ in series with a resistance $R_\text{th}$ (Thévenin), or equivalently a current source $I_\text{N}$ in parallel with $R_\text{th}$ (Norton), with

\[ V_\text{th}=v_\text{oc}\ \text{(open-circuit voltage)}, \quad I_\text{N}=i_\text{sc}\ \text{(short-circuit current)}, \quad R_\text{th}=\frac{v_\text{oc}}{i_\text{sc}}. \]

$R_\text{th}$ can also be found by deactivating all independent sources and computing the resistance seen at the port. The equivalence is exact for any external load — this is what makes it so powerful. Every signal source in the rest of the course (function generator, sensor, amplifier output) is modeled as a Thévenin source, and every input as a load.

Maximum power transfer

A Thévenin source $（V_\text{th}, R_\text{th})$ delivers maximum power to a load when $R_L=R_\text{th}$, at which point the load power is $V_\text{th}^2/(4R_\text{th})$ and efficiency is exactly 50%. This matched condition matters for power delivery and RF, but note: for signal delivery we usually want $R_L \gg R_\text{th}$ (maximize voltage, not power) — a distinction that explains why amplifier inputs are high-impedance.

Theory Exercises

Derive the voltage-divider and current-divider formulas from KVL/KCL and Ohm’s law.
For a given 4–5 resistor network, set up nodal analysis: write the conductance matrix $\mathbf{G}$ by inspection and solve $\mathbf{G}\mathbf{v}=\mathbf{i}$.
Solve the same network by mesh analysis and confirm identical branch currents.
Apply superposition to a two-source network; verify the sum equals the direct solution. Then show explicitly that superposing the individual power dissipations gives the wrong total power.
Prove the Thévenin theorem for a network with one independent source (use superposition + linearity), and derive $R_\text{th}=v_\text{oc}/i_\text{sc}$.
Derive the maximum-power-transfer condition $R_L=R_\text{th}$ by differentiating load power with respect to $R_L$.
A 5 V source feeds a $10\,\text{k}\Omega$ / $10\,\text{k}\Omega$ divider. Compute the output (a) unloaded and (b) loaded by a $10\,\text{k}\Omega$ load. Quantify the loading error.

Lab / Bench Work

Divider + loading: Build a $10\,\text{k}\Omega$/$10\,\text{k}\Omega$ divider from 5 V. Measure the unloaded mid-node voltage, then load it with another $10\,\text{k}\Omega$ and measure again. Confirm the measured drop matches the $R_2\parallel R_L$ prediction. This is the most important practical lesson of the week.

Thévenin equivalence proof: Build a network of 4–5 resistors with the 5 V source, exposing one port. (1) Measure $v_\text{oc}$ (open-circuit, voltmeter only). (2) Measure $i_\text{sc}$ (short the port through the ammeter — confirm the network can’t be damaged by this first). (3) Compute $R_\text{th}=v_\text{oc}/i_\text{sc}$. (4) Build the two-component Thévenin equivalent ($V_\text{th}$ via a divider, $R_\text{th}$ the nearest kit resistor). (5) Load both the original and the equivalent with a sweep of load resistors (use the potentiometer) and show the load voltage matches at every setting.

Qucs-S (ngspice) cross-check: Draw the full network in Qucs-S and run the ngspice .op and a .dc sweep of the load, overlaying the simulated load-voltage curve with your measured points.

Measurement Methodology

For $v_\text{oc}$, the voltmeter’s finite input impedance ($$10 M$$) is itself a load; confirm it is $\gg R_\text{th}$ so the reading is truly open-circuit.
For $i_\text{sc}$, the ammeter’s small series resistance and the source’s real internal resistance both perturb the measurement — note them and decide whether they matter at your tolerance.
Use the potentiometer as a continuously variable load and measure with the Fluke; record load voltage vs measured pot resistance. The original and Thévenin equivalent should track within resistor tolerance across the whole sweep.
Reconcile hand solution, Qucs-S .op, and measurement for at least the open-circuit voltage and one loaded point.

Expected baselines: Node voltages agree with Qucs-S (ngspice) to 3+ significant figures (both solve the same linear system); measurement within ±5% set by resistor tolerance. The Thévenin equivalent and original network should produce load voltages indistinguishable within tolerance — the entire point of the lab.

Connections

Series/parallel reduction and the divider recur constantly: biasing networks (Week 7), filter design (Week 6), and source/load impedance reasoning everywhere. Superposition is the linear-systems property that becomes Fourier superposition of sinusoids in Week 8. Thévenin/Norton equivalents are the abstraction for treating each course block as a source driving a load; output impedance vs input impedance is the recurring design tension that motivates the op-amp buffer in Week 7. Nodal analysis is literally how ngspice (the engine behind Qucs-S) works, so understanding it demystifies the simulator you will lean on all course.